With a common process for forming a pattern in fabrication of a semiconductor device, a workpiece film on which a pattern is formed is first formed on the entire surface of a semiconductor substrate, and subsequently, a photo resist film is first formed on the entire surface of the workpiece film. Thereafter, the photo resist film is patterned by the well known photolithographic techniques. A resist pattern formed after being patterned as above is used as a mask in etching of the workpiece film that is an underlying film. Subsequently, the photo resist film is removed, whereupon a pattern of the workpiece film is formed on the semiconductor substrate.
Following a recent increase in the degree of integration in a semiconductor device, miniaturization is required of the minimum line width of the semiconductor device. In order to meet such requirements, it is important to form a superfine resist pattern. However, there has arisen a problem in that requirements for miniaturization beyond a resolution limit cannot be met by use of the conventional photolithographic techniques because there exists a resolution limit due to a wavelength of exposure light used in the formation of a resist pattern.
As a method for overcoming the problem described, there has thus far been available, for example, a process for forming a resist pattern as disclosed in the public known patent document (JP-A 2002-23390).
The related art as disclosed in JP-A 2002-23390 is described hereinafter.
With techniques for miniaturization of a resist pattern as disclosed in the patent document, a resist pattern with a size larger than a final target value (target size) for a finished pattern is first formed in the step of applying photolithographic techniques. Subsequently, the resist pattern is miniaturized to a desired size (the target size) by applying ashing thereto, thereby obtaining a resist pattern with a size smaller than a resolution limit due to a wavelength of exposure light.
However, with the conventional techniques for miniaturization of a resist pattern, a problem has been encountered in that nonuniformity of plasma occurs at the time ashing is applied to the resist pattern, due to a difference in atmosphere inside a plasma chamber, and variation in chemical species. As a result, a pattern shift is susceptible to variation in a wafer surface and among a plurality of wafers, and there has occurred fluctuation in the size of the resist pattern after the ashing. More specifically, with the conventional techniques for miniaturization of a resist pattern, it has been difficult to achieve highly accurate control of size, resulting in occurrence of a problem of deterioration in chip reliability and yield, caused by deterioration in size accuracy.